VZEROALL — Zero All YMM Registers

Opcode/Instruction Op/En 64/32 bit Mode Support CPUID Feature Flag Description
VEX.256.0F.WIG 77 VZEROALL ZO V/V AVX Zero all YMM registers.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4


The instruction zeros contents of all XMM or YMM registers.

Note: VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. In Compatibility and legacy 32-bit mode only the lower 8 registers are modified.


simd_reg_file[][] is a two dimensional array representing the SIMD register file containing all the overlapping xmm, ymm and zmm
registers present in that implementation. The major dimension is the register number: 0 for xmm0, ymm0 and zmm0; 1 for xmm1,
ymm1, and zmm1; etc. The minor dimension size is the width of the implemented SIMD state measured in bits. On a machine
supporting Intel AVX-512, the width is 512. On a machine supporting Intel AVX but not Intel AVX-512, the width is “MAXVL”.

VZEROALL (VEX.256 encoded version)

IF (64-bit mode)
    limit ←15
    limit ← 7
FOR i in 0 .. limit:
    simd_reg_file[i][MAXVL-1:0] ← 0

Intel C/C++ Compiler Intrinsic Equivalent

VZEROALL: _mm256_zeroall()

SIMD Floating-Point Exceptions


Other Exceptions

See Exceptions Type 8.